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? semiconductor components industries, llc, 2017 october, 2017 ? rev. 7 1 publication order number: NCP1060/d NCP1060, ncv1060, ncp1063, ncv1063 high-voltage switcher for low power offline smps the ncp106x products integrate a fixed frequency current mode controller with a 700 v mosfet. available in a pdip?7, soic?10 or soic?16 package, the ncp106x offer a high level of integration, including soft?start, frequency?jittering, short?circuit protection, skip?cycle, adjustable peak current set point, ramp compensation, and a dynamic self?supply (eliminating the need for an auxiliary winding). unlike other monolithic solutions, the ncp106x is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (60 khz or 100 khz). when the output power demand diminishes, the ic automatically enters frequency foldback mode and provides excellent efficiency at light loads. when the power demand reduces further, it enters into a skip mode to reduce the standby consumption down to a no load condition. protection features include: a timer to detect an overload or a short?circuit event, overvoltage protection with auto?recovery and ac input line voltage detection (a version). the on proprietary integrated over power protection (opp) lets you harness the maximum delivered power without affecting your standby performance simply via external resistors. for improved standby performance, the connection of an auxiliary winding stops the dss operation and helps to reduce input power consumption below 50 mw at high line. ncp106x can be seamlessly used both in non?isolated and in isolated topologies. features ? built?in 700 v mosfet with r ds(on) of 34 (NCP1060) and 11.4 (ncp1063) ? large creepage distance between high?voltage pins ? current?mode fixed frequency operation ? 60 khz or 100 khz (130 khz on demand) ? adjustable peak current: see below table ? fixed ramp compensation ? direct feedback connection for non?isolated converter ? internal and adjustable over power protection (opp) circuit ? skip?cycle operation at low peak currents only ? dynamic self?supply: no need for an auxiliary winding ? internal 4 ms soft?start ? auto?recovery output short circuit protection with timer?based detection ? auto?recovery overvoltage protection with auxiliary winding operation ? frequency jittering for better emi signature ? no load input consumption < 50 mw ? frequency foldback to improve efficiency at light load ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free and are rohs compliant typical applications ? auxiliary / standby isolated and non?isolated power supplies ? power meter smps ? wide vin low power industrial smps www. onsemi.com pdip?7 case 626a ap suffix 1 8 marking diagrams see detailed ordering and shipping information in the package dimensions section on page 28 of this data sheet. ordering information soic?10 case 751bq ad or bd suffix soic?16 case 751b?05 d suffix 1 10 x = power switch circuit on?state resistance x = (0 = 34 , 3 = 11.4 ) f = brown in (a = yes, b = no) yyy = oscillator frequency yyy = (060 = 60 khz, 100 = 100 khz) z = p (standard) or v (automotive) u = blank (standard) or v (automotive) a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb?free package p106xfyyy awl yywwg u1060fyyy alywx 1 10 ncz1063fyyyg awlyww 1 16 1 16 1 7
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 2 product information & indicative maximum output power product r ds(on) i ipk(0) 230 vac 15% 85 ? 265 vac adapter open frame adapter open frame NCP1060 60 khz 34 300 ma 3.3 w 8.3 w 1.9 w 4.7 w ncp1063 100 khz 11.4 780 ma 6.2 w 15.5 w 3.3 w 7.8 w note: informative values only, with t amb = 25 c, t case = 100 c, pdip?7 package, self supply via auxiliary winding and circuit mounted on minimum copper area as recommended. pdip?7 drain drain comp gnd vcc lim/opp fb soic?16 drain drain drain drain n.c. n.c. n.c. n.c. gnd gnd gnd gnd vcc lim/opp fb comp soic?10 drain drain drain drain gnd vcc lim/opp fb comp drain figure 1. pin connections table 1. pin function description pin no pin name function pin description pdip 7 soic 10 soic 16 1 1 1?4 gnd the ic ground 2 2 5 v cc powers the internal circuitry this pin is connected to an external capacitor. the v dd includes an auto?recovery over voltage protection. 3 3 6 lim/opp ipeak set / over power limitation the current drown from the pin decreases ipeak of the primary winding. if resistive divider from the auxiliary winding is connected to this pin it sets the opp compen- sation level (it diminishes the peak current.) 4 4 7 fb feedback signal input this is the inverting input of the trans conductance error amplifier. it is normally connected to the switching power supply output through a resistor divider. 5 5 8 comp compensation the error amplifier output is available on this pin. the network connected between this pin and ground adjusts the regulation loop bandwidth. also, by connecting an opto?coupler to this pin, the peak current set point is adjusted accordingly to the output power demand. 6 9?12 this un?connected pin ensures adequate creepage dis- tance 7,8 6?10 13?16 drain drain connection the internal drain mosfet connection
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 3 table 2. typical applications ? if the output voltage is above 9.0 v typ. between v cc(on) level and v ovp level ? vcc supplied from output via d2 ? r2 limits maximal output power ? direct feedback, resistive divider formed by r3, r4 sets output voltage ? vcc supplied from dss ? output voltage is below 9.0 v typ. ? lim/opp pin floating ? no limit output power ? optocoupler feedback typical non?isolated application ? buck converter ? if the output voltage is above 9.0 v typ. between v cc(on) level and v ovp level ? vcc supplied from output via d2 ? r2 limits maximal output power ? direct feedback, resistive divider formed by r3, r4 sets output voltage ? vcc supplied from dss ? output voltage is below 9.0 v typ. ? lim/opp pin floating ? no limit output power ? direct feedback, resistive divider formed by r2, r3 sets output voltage typical non?isolated application ? buck?boost converter
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 4 table 2. typical applications ? vcc supplied from dss ? output voltage is below 9.0 v typ. ? lim/opp pin floating ? no limit output power ? resistive divider formed by r2, r3 sets output volt- age ? if the output voltage is above 9.0 v typ. between v cc(on) level and v ovp level ? vcc supplied from output via d4 ? lim/opp pin floating ? no limit output power ? resistive divider formed by r2, r3 sets output volt- age typical non?isolated application ? flyback converter ? vcc supplied from auxil- iary winding ? resistive divider formed by r2, r3 sets output pow- er limit and over power protection ? optocoupler feedback, re- sistive divider formed by r6, r7 sets output voltage typical isolated application ? flyback converter
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 5 lim/opp fb comp gnd drain vcc s r q vcc management reset uvlo v dd t scp i pflag scp t recovery 80? s filter line detection off uvlo s r q r comp(up) uvlo tsd leb soft? start reset reset ss as recoving from scp, tsd, vcc ovp or uvlo i comp to cs setpoint i freeze i pk(0) v cc osc sawtooth foldback lineok lineok sawtooth i pflag ramp compensation off v cc ovp skip = ?1? shut down some blocks to reduce consumption skip i lmop v lmop i lmdec i lmdec i lmop 0 i pkl i fb v comp(ref ) i compskip i compfault i lmop (min) i lmop (max ) jittering v ovp fb/comp processing figure 2. simplified internal circuit architecture
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 6 table 3. maximum rating table (all voltages related to gnd terminal) rating symbol value unit power supply voltage, v cc pin, continuous voltage v cc ?0.3 to 20 v voltage on all pins, except drain and v cc pin vinmax ?0.3 to 10 v drain voltage bvdss ?0.3 to 700 v maximum current into v cc pin i cc 10 ma drain current peak during transformer saturation (t j = 150 c, note 2): NCP1060 ncp1063 drain current peak during transformer saturation (t j = 125 c, note 2): NCP1060 ncp1063 drain current peak during transformer saturation (t j = 25 c, note 2): NCP1060 ncp1063 i ds(pk) 300 850 335 950 520 1500 ma thermal resistance junction?to?air ? pdip7 with 200 mm of 35? copper area r ja 115 c/w thermal resistance junction?to?air ? soic10 with 200 mm of 35? copper area r ja 132 c/w thermal resistance junction?to?air ? soic16 with 200 mm of 35? copper area r ja 104 c/w junction temperature range t j ?40 to +150 c storage temperature range t stg ?60 to +150 c human body model esd capability (all pins except hv pin) per jedec jesd22?a114f hbm 2 kv charged?device model esd capability per jedec jesd22?c101e cdm 1 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. 2. maximum drain current i ds(pk) is obtained when the transformer saturates. it should not be mixed with short pulses that can be seen at turn on. figure 3 below provides spike limits the device can tolerate. figure 3. spike limits
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 7 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 14 v unless otherwise noted) symbol rating pin min typ max unit supply section and v cc management v cc(on) v cc increasing level at which the switcher starts operation 2 (5) 8.4 9.0 9.5 v v cc(min) v cc decreasing level at which the hv current source restarts 2 (5) 7.0 7.5 7.8 v v cc(off) v cc decreasing level at which the switcher stops operation (uvlo) 2 (5) 6.7 7.0 7.2 v i cc1 internal ic consumption, NCP1060 switching at 60 khz, lim/opp = 0 a internal ic consumption, NCP1060 sw itching at 100 khz, lim/opp = 0 a internal ic consumption, ncp1063 switching at 60 khz, lim/opp = 0 a internal ic consumption, ncp1063 sw itching at 100 khz, lim/opp = 0 a 2 (5) ? ? ? ? 0.92 0.97 0.99 1.07 ? ? ? ? ma i ccskip internal ic consumption, comp is 0 v (no switching on mosfet) 2 (5) ? 340 ? a power switch circuit r ds(on) power switch circuit on?state resistance NCP1060 (id = 50 ma) tj = 25 c tj = 125 c ncp1063 (id = 50 ma) tj = 25 c tj = 125 c 7, 8 (6?10) (13?16) ? ? ? ? 34 65 11.4 22 41 72 14.0 24 bv dss power switch circuit & startup breakdown voltage (id (off) = 120 a, tj = 25 c) 7, 8 (6?10) (13?16) 700 ? ? v i dss(off) power switch & startup breakdown voltage off?state leakage current tj = 125 c (vds = 700 v) 7, 8 (6?10) (13?16) ? 84 ? a t r t f switching characteristics (r l = 50 , v ds set for i drain = 0.7 x ilim) turn?on time (90% ? 10%) turn?off time (10% ? 90%) 7, 8 (6?10) (13?16) ? ? 20 10 ? ? ns t on(min) minimum on time NCP1060 ncp1063 7, 8 (6?10) (13?16) ? ? 200 230 ? ? ns internal start?up current source i start1 high?voltage current source, v cc = v cc(on) ? 200 mv 7, 8 (6?10) (13?16) 5 8 12 ma i start2 high?voltage current source, v cc = 0 v 7, 8 (6?10) (13?16) ? 0.5 ? ma v ccth v cc transient level for i start1 to i start2 toggling point 2 (5) ? 1.4 ? v v start(min) minimum startup voltage, v cc = 0 v 7, 8 (6?10) (13?16) 21 v current comparator i ipk maximum internal current setpoint at 50% duty cycle fb = 2 v, lim/opp = 0 a, tj = 25 c NCP1060 ncp1063 ? ? ? ? 250 650 ? ? ma i ipk(0) maximum internal current setpoint at beginning of switching cycle fb = 2 v, lim/opp pin open tj = 25 c NCP1060 ncp1063 ? ? 268 702 300 780 332 858 ma 3. the final switch current is: i ipk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built?in slope compensation, vin the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. oscillator frequency is measured with disabled jittering.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 8 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 14 v unless otherwise noted) symbol unit max typ min pin rating current comparator i ipksw final switch current with a primary slope of 200 ma/ s, f sw = 60 khz (note 3), lim/opp pin open NCP1060 ncp1063 ? ? ? ? 330 740 ? ? ma i ipksw final switch current with a primary slope of 200 ma/ s, f sw = 100 khz (note 3), lim/opp pin open NCP1060 ncp1063 ? ? ? ? 320 710 ? ? ma i lmdec maximum internal current setpoint at beginning of switching cycle fb = 2 v, lim/opp = ?285 a, tj = 25 c NCP1060 ncp1063 ? ? ? ? 128 312 ? ? ma t ss soft?start duration (guaranteed by design) ? ? 4 ? ms t prop propagation delay from current detection to drain off state ? ? 70 ? ns t leb leading edge blanking duration NCP1060 ncp1063 ? ? ? ? 130 160 ? ? ns internal oscillator f osc oscillation frequency, 60 khz version, tj = 25 c (note 4) ? 54 60 66 khz f osc oscillation frequency, 100 khz version, tj = 25 c (note 4) ? 90 100 110 khz f jitter frequency jittering in percentage of f osc ? ? 6 ? % f swing jittering swing frequency ? ? 300 ? hz d max maximum duty?cycle ? 62 66 72 % error amplifier section v ref voltage feedback input (v comp = 2.5 v) 4 (7) 3.2 3.3 3.4 v i fb input bias current (v fb = 3.3 v) 4 (7) ? 1 ? a g m transconductance 5 (8) 2 ms i otalim ota maximum current capability (v fb > v otaen ) 5 (8) 150 a v otaen fb voltage to disable ota 4 (7) 0.7 1.3 1.7 v compensation section i compfault comp current for which fault is detected 5 (8) ? ?40 ? a i comp100% comp current for which internal current set?point is 100% (i ipk(0) ) 5 (8) ? ?44 ? a i compfreeze comp current for which internal current setpoint is: i freeze1 or 2 (NCP1060/3) 5 (8) ? ?80 ? a v comp(ref) equivalent pull?up voltage in linear regulation range (guaranteed by design) 5 (8) ? 2.7 ? v r comp(up) equivalent feedback resistor in linear regulation range (guaranteed by design) 5 (8) ? 17.7 ? k ? v lmop voltage on lim/opp pin @ i lmop = ?35 a voltage on lim/opp pin @ i lmop = ?250 a, tj = 25 c 3 (6) 1.40 1.28 1.50 1.35 1.60 1.42 v i lmop maximum current from lim/opp pin 3 (6) ?330 ?420 a i lmop(min) current at which lim/opp starts to decrease i peak 3 (6) ?20 ?26 ?32 a i lmop(max) current at which lim/opp stops to decrease i peak 3 (6) ?285 a i lmop(neg) negative active clamp voltage (i lmop = ?2.5 ma) 3 (6) ?0.7 v 3. the final switch current is: i ipk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built?in slope compensation, vin the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. oscillator frequency is measured with disabled jittering.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 9 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 14 v unless otherwise noted) symbol unit max typ min pin rating compensation section i lmop(pos) positive active clamp (guaranteed by design) 3 (6) 2.5 ma frequency foldback & skip i compfold start of frequency foldback comp pin current level 5 (8) ? ?68 ? a i compfold(end) end of frequency foldback comp pin current level, f sw = f min 5 (8) ? ?100 ? a f min the frequency below which skip?cycle occurs ? 21 25 29 khz i compskip the comp pin current level to enter skip mode 5 (8) ? ?120 ? a i freeze1 internal minimum current setpoint (i comp = i compfreeze ) in NCP1060 ? 110 ? ma i freeze2 internal minimum current setpoint (i comp = i compfreeze ) in ncp1063 ? 270 ? ma ramp compensation s a(60) the internal ramp compensation @ 60 khz: NCP1060 ncp1063 ? ? ? ? 8.4 15.6 ? ? ma/ s s a(100) the internal ramp compensation @ 100 khz: NCP1060 ncp1063 ? ? ? ? 14 26 ? ? ma/ s protections t scp fault validation further to error flag assertion ? 35 48 ? ms t recovery off phase in fault mode ? ? 400 ? ms v ovp v cc voltage at which the switcher stops pulsing 2 (5) 17.0 18.0 18.8 v t ovp the filter of v cc ovp comparator ? ? 80 ? s v hv(en) the drain pin voltage above which allows mosfet operate, which is detected after tsd, uvlo, scp, or v cc ovp mode. (a version only) 7,8 (6?10) (13?16) 67 87 110 v temperature management tsd temperature shutdown (guaranteed by design) ? 150 163 ? c tsd hyst hysteresis in shutdown (guaranteed by design) ? ? 20 ? c 3. the final switch current is: i ipk(0) / (v in /l p + s a ) x v in /l p + v in /l p x t prop , with s a the built?in slope compensation, vin the input voltage, l p the primary inductor in a flyback, and t prop the propagation delay. 4. oscillator frequency is measured with disabled jittering. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 10 typical characteristics figure 4. v cc(on) vs. temperature figure 5. v cc(min) vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 8.85 8.90 8.95 9.00 9.05 9.10 9.15 100 80 60 40 20 0 ?20 ?40 7.32 7.34 7.38 7.42 7.46 7.48 7.52 figure 6. v cc(off) vs. temperature figure 7. i dss(off) vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 6.88 6.90 6.92 6.94 6.96 6.98 7.00 100 80 60 40 20 0 ?20 ?40 0 100 200 300 400 600 700 800 figure 8. i cc1 60 khz vs. temperature figure 9. i cc1 100 khz vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 100 80 60 40 20 0 ?20 ?40 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 voltage (v) voltage (v) voltage (v) current ( a) current (ma) current (ma) 120 120 120 7.36 7.40 7.44 7.50 120 500 120 120
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 11 typical characteristics figure 10. i ipk(0)1060 vs. temperature figure 11. i ipk(0)1063 vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 288 292 294 296 300 304 306 310 100 80 60 40 20 0 ?20 ?40 720 725 735 740 750 755 765 770 figure 12. i start1 vs. temperature figure 13. i start2 vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 0 2 4 8 10 12 100 80 60 40 20 0 ?20 ?40 0 0.1 0.2 0.3 0.4 0.5 0.6 figure 14. r ds(on)1060 vs. temperature figure 15. r ds(on)1063 vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 0 10 20 30 40 50 60 70 100 80 60 40 20 0 ?20 ?40 0 5 10 15 20 25 current (ma) current (ma) current (ma) current (ma) resistivity ( ) resistivity ( ) 120 290 298 302 308 120 730 745 760 120 6 120 120 120
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 12 typical characteristics figure 16. f osc60 vs. temperature figure 17. f osc100 vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 55.5 56.0 57.0 57.5 58.0 58.5 59.5 60.0 100 80 60 40 20 0 ?20 ?40 92 93 94 95 96 98 99 100 figure 18. i freeze1060 vs. temperature figure 19. i freeze1063 vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 100 101 103 104 105 106 108 109 100 80 60 40 20 0 ?20 ?40 256 258 262 264 266 268 272 274 figure 20. d (max) vs. temperature figure 21. f min vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 65.6 65.7 65.8 65.9 66.0 66.1 66.2 100 80 60 40 20 0 ?20 ?40 24.4 24.6 24.8 25.0 25.2 25.4 25.6 25.8 frequency (khz) frequency (khz) current (ma) current (ma) duty cycle (%) frequency (khz) 120 56.5 59.0 120 97 120 102 107 120 260 270 120 120
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 13 typical characteristics figure 22. t recovery vs. temperature figure 23. t scp vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 385 390 400 405 410 415 425 430 100 80 60 40 20 0 ?20 ?40 46 47 48 49 50 51 52 53 figure 24. v ovp vs. temperature figure 25. v hv(en) vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 17.4 17.5 17.6 17.8 17.9 18.0 18.1 18.2 100 80 60 40 20 0 ?20 ?40 84 85 86 87 88 90 91 92 figure 26. v ref vs. temperature figure 27. v otaen vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 3.24 3.26 3.27 3.28 3.30 3.31 3.33 3.34 100 80 60 40 20 0 ?20 ?40 0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 time (ms) time (ms) voltage (v) voltage (v) voltage (v) voltage (v) 120 395 420 120 120 89 120 17.7 120 3.25 3.29 3.32 120 1.0
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 14 typical characteristics figure 28. drain current peak during transformer saturation vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 1.0 1.5 2.5 i ds(pk) (a) 150 0.5 2.0 ncp1063 NCP1060 figure 29. breakdown voltage vs. temperature temperature ( c) 100 60 40 20 0 ?20 ?40 0.925 0.950 0.975 1.025 1.050 1.100 bv dss /bv dss (25 c)(?) 125 1.000 80 1.075
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 15 application information introduction the ncp106x offers a complete current?mode control solution. the component integrates everything needed to build a rugged and cost effective switch?mode power supply (smps) featuring low standby power. the quick selection table, table 5, details the differences between references, mainly peak current setpoints, r ds(on) value and operating frequency. ? current?mode operation: the controller uses current?mode control architecture. ? 700 v ?_ power mosfet: due to on semiconductor very high voltage integrated circuit technology, the circuit hosts a high?voltage power mosfet featuring a 34 or 11.4 r ds(on) ? tj = 25 c. this value lets the designer build a power supply up to 7.8 w or 15.5 w operated on universal mains. an internal current source delivers the startup current, necessary to crank the power supply. ? dynamic self?supply: due to the internal high voltage current source, this device could be used in the application without the auxiliary winding to provide supply voltage. ? short circuit protection: by permanently monitoring the comp line activity, the ic is able to detect the presence of a short?circuit, immediately reducing the output power for a total system protection. a t scp timer is started as soon as the comp current is below threshold, i compfault , which indicates the maximum peak current. if at the end of this timer the fault is still present, then the device enters a safe, auto?recovery burst mode, affected by a fixed timer recurrence, t recovery . once the short has disappeared, the controller resumes and goes back to normal operation. ? built?in vcc over v oltage protection: when the auxiliary winding is used to bias the v cc pin (no dss), an internal comparator is connected to v cc pin. in case the voltage on the pin exceeds a level of v ovp (18 v typically), the controller immediately stops switching and waits a full timer period (t recovery ) before attempting to restart. if the fault is gone, the controller resumes operation. if the fault is still there, e.g. a broken opto?coupler, the controller protects the load through a safe burst mode. ? line detection: an internal comparator monitors the drain voltage as recovering from one of the following situations: ? short circuit protection, ? v cc ovp is confirmed, ? uvlo, ? tsd ? if the drain voltage is lower than the internal threshold (v hv(en) ), the internal power switch is inhibited. this avoids operating at too low ac input. this is also called brown?in function in some fields. for applications not using standard ac mains (24 vdc industrial bus for instance), the b version doesn?t incorporate this line detection and let the device start as soon as voltage supply reaches v start(min). ? frequency jittering: an internal low?frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering remains active in frequency foldback mode. ? soft?start: a 4 ms soft?start ensures a smooth startup sequence, reducing output overshoots. ? frequency foldback capability: a continuous flow of pulses is not compatible with no?load/light?load standby power requirements. to excel in this domain, the controller observes the comp pin current information and when it reaches a level of i compfold , the oscillator then starts to reduce its switching frequency as the feedback current continues to increase (the power demand continues to reduce). it can go down to 25 khz (typical) reached for a feedback level of i compfold(end) (100 a roughly). at this point, if the power continues to drop, the controller enters classical skip?cycle mode. ? skip: if smps naturally exhibits a good efficiency at nominal load, it begins to be less efficient when the output power demand diminishes. by skipping un?needed switching cycles, the ncp106x drastically reduces the power wasted during light load conditions. ? ipeak set: if current in range 26 a and 285 a is drawn from the pin, the peak current is proportionally reduced down to 40% of its original value. this feature enables to designer to set up the peak current to the value which is ideal for the application. by routing a portion of the negative voltage present during the on?time on the auxiliary winding to the lim/opp pin, the user has a simple and non?dissipative means to alter the maximum peak current setpoint as the bulk voltage increases.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 16 application information startup sequence when the power supply is first powered from the mains outlet, the internal current source (typically 8.0 ma) is biased and charges up the v cc capacitor from the drain pin. once the voltage on this v cc capacitor reaches the v cc(on) level (typically 9.0 v), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power mosfet if the bulk voltage is above v hv(en) level (87 v typically) for a version and if bulk voltage is above v start(min) (21 v dc) for b version. figure 30 details the simplified internal circuitry. + ? v cc(on) v cc(min) i start1 v bulk 5 8 1 c vcc r limit i1 i cc1 i2 vcc > 18 v ? ovp fault drain +? v ovp figure 30. the internal arrangement of the start?up circuitry being loaded by the circuit consumption, the voltage on the v cc capacitor goes down. when v cc is below v cc(min) level (7.5 v typically), it activates the internal current source to bring v cc toward v cc(on) level and stops again: a cycle takes place whose low frequency depends on the v cc capacitor and the ic consumption. a 1.5 v ripple takes place on the v cc pin whose average value equals (v cc(on) + v cc(min) )/2. figure 31 portrays a typical operation of the dss.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 17 0 1 2 3 4 5 6 7 8 9 10 012345678910 v cc 9.0 v v ccth startup duration figure 31. the charge/discharge cycle over a 1 f v cc capacitor device internal pulses 7.5 v time (ms) v (v) as one can see, even if there is auxiliary winding to provide energy for v cc , it happens that the device is still biased by dss during start?up time or some fault mode when the voltage on auxiliary winding is not ready yet. the v cc capacitor shall be dimensioned to avoid v cc crosses v cc(off) level, which stops operation. the v between v cc(min) and v cc(off) is 0.5 v. there is no current source to charge v cc capacitor when driver is on, i.e. drain voltage is close to zero. hence the v cc capacitor can be calculated using c vcc i cc1 d max f osc v (eq. 1) take the 60 khz device as an example. c vcc should be above 0.8 m 72% 54 khz 0.5 21 nf. a margin that covers the temperature drift and the voltage drop due to switching inside fet should be considered, and thus a capacitor above 0.1 f is appropriate. the v cc capacitor has only a supply role and its value does not impact other parameters such as fault duration or the frequency sweep period for instance. as one can see on figure 30, an internal ovp comparator, protects the switcher against lethal v cc runaways. this situation can occur if the feedback loop optocoupler fails, for instance, and you would like to protect the converter against an over voltage event. in that case, the over voltage protection (ovp) circuit and immediately stops the output pulses for t recovery duration (400 ms typically). then a new start?up attempt takes place to check whether the fault has disappeared or not. the ovp paragraph gives more design details on this particular section. fault condition ? short?circuit on v cc in some fault situations, a short?circuit can purposely occur between v cc and gnd. in high line conditions (v hv = 370 v dc ) the current delivered by the startup device will seriously increase the junction temperature. for instance, since i start1 equals 5 ma (the min corresponds to the highest t j ), the device would dissipate 370 x 5 m = 1.85 w. to avoid this situation, the controller includes a novel circuitry made of two startup levels, i start1 and i start2 . at power?up, as long as v cc is below a 1.4 v level, the source delivers i start2 (around 500 a typical), then, when v cc reaches 1.4 v, the source smoothly transitions to i start1 and delivers its nominal value. as a result, in case of short?circuit between v cc and gnd, the power dissipation will drop to 370 x 500 = 185 mw. figure 31 portrays this particular behavior. the first startup period is calculated by the formula c x v = i x t, which implies a 1 x 1.4 / 500 = 2.8 ms startup time for the first sequence. the second sequence is obtained by toggling the source to 8 ma with a delta v of v cc(on) ? v ccth = 9.0 ? 1.4 = 7.6 v, which finally leads to a second startup time of 1 x 7.6 / 8 m = 0.95 ms. the total startup time becomes 2.8 m + 0.95 m = 3.75 ms. please note that this calculation is approximated by the presence of the knee in the vicinity of the transition.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 18 fault condition ? output short?circuit as soon as v cc reaches v cc(on) , drive pulses are internally enabled. if everything is correct, the auxiliary winding increases the voltage on the v cc pin as the output voltage rises. during the start?sequence, the controller smoothly ramps up the peak drain current to maximum setting, i.e. i ipk , which is reached after a typical period of 4 ms. when the output voltage is not regulated, the current coming through comp pin is below i compfault level (40 a typically), which is not only during the startup period but also anytime an overload occurs, an internal error flag is asserted, ipflag, indicating that the system has reached its maximum current limit set point. the assertion of this flag triggers a fault counter t scp (48 ms typically). if at counter completion, i pflag remains asserted, all driving pulses are stopped and the part stays off in t recovery duration (about 400 ms). a new attempt to re?start occurs and will last 48 ms providing the fault is still present. if the fault still affects the output, a safe burst mode is entered, affected by a low duty?cycle operation (11%). when the fault disappears, the power supply quickly resumes operation. figure 32 depicts this particular mode: figure 32. in case of short?circuit or overload, the ncp106x protects itself and the power supply via a low frequency burst mode. the v cc is maintained by the current source and self?supplies the controller. ipflag timer drv internal 48 ms typ. 400 ms typ. fault open loop fb v cc(on) v cc(min) v cc v comp auto?recovery over voltage protection the particular ncp106x arrangement offers a simple way to prevent output voltage runaway when the optocoupler fails. as figure 33 shows, a comparator monitors the v cc pin. if the auxiliary pushes too much voltage into the c vcc capacitor, then the controller considers an ovp situation and stops the internal drivers. when an ovp occurs, all switching pulses are permanently disabled. after t recovery delay, it resumes the internal drivers. if the failure symptom still exists, e.g. feedback opto?coupler fails, the device keeps the auto?recovery ovp mode. it is recommended insertion of a resistor ( r limit ) between the a uxiliary dc level and the v cc pin to protect the ic against high voltage spikes, which can damage the ic, and to filter out the vcc line to avoid undesired ovp activation. r limit should be carefully selected to avoid triggering the ovp as we discussed, but also to avoid disturbing the v cc in low / light load conditions. self?supplying controllers in extremely low standby applications often puzzles th e designer. actually, if a smps operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 v (v nom ), this voltage can drop below 10 v (v stby ) when entering standby. this is because the recurrence of the switching pulses expands so much that the low frequency re?fueling rate of the v cc capacitor is not enough to keep a proper auxiliary voltage.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 19 v ovp gnd v cc drain shut down internal drv 80 s filter v cc (on ) =9.0v v cc (min ) =7.5v i start 1 r limit d1 c vcc c aux n aux figure 33. a more detailed view of the ncp106x offers better insight on how to properly wire an auxiliary winding v cc i comp timer drv internal v cc(min) v cc(on) v ovp fault level 48 ms typ. 400 ms typ. figure 34. describes the main signal variations when the part operates in auto?recovery ovp: soft?start the ncp106x features a 4 ms soft?start which reduces the power?on stress but also contributes to lower the output overshoot. figure 35 shows a typical operating waveform. the ncp106x features a novel patented structure which offers a better soft?start ramp, almost ignoring the start?up pedestal inherent to traditional current?mode supplies.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 20 drain current v cc v ccon max ip 4ms 0v (fresh pon) figure 35. the 4 ms soft?start sequence jittering frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. the ncp106x offers a 6% deviation of the nominal switching frequency. the sweep sawtooth is internally generated and modulates the clock up and down with a fixed frequency of 300 hz. figure 36 shows the relationship between the jitter ramp and the frequency deviation. it is not possible to externally disable the jitter. 60 khz 63.6 khz 56.4 khz jitter ramp internal sawtooth adjustable figure 36. modulation effects on the clock signal by the jittering sawtooth line detection (for a version only) an internal comparator monitors the drain voltage as recovering from one of the following situations: ? short circuit protection, ? v cc ovp is confirmed, ? uvlo ? tsd if the drain voltage is lower than the internal threshold v hv(en) (87 vdc typically), the internal power switch is inhibited. this avoids operating at too low ac input.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 21 frequency foldback the reduction of no?load standby power associated with the need for improving the ef ficiency, requires to change the traditional fixed?frequency type of operation. this device implements a switching frequency foldback when the comp current passes above a certain level, i compfold , set around 68 a. at this point, the oscillator enters frequency foldback and reduces its switching frequency. the internal peak current set?point is following the comp current information until its level reaches i freeze . below this value, the peak current setpoint is frozen to 30% of the i pk(0) . the only way to further reduce the transmitted power is to diminish the operating frequency down to f min (25 khz typically). this value is reached at a comp current level of i compfold(end) (100 a typically). below this point, if the output power continues to decrease, the part enters skip cycle for the best noise?free performance in no?load conditions. figure 37 and figure 38 depict the adopted scheme for the part. figure 37. by observing the current on the comp pin, the controller reduces its switching frequency for an improved performance at light load. 0 10 20 30 40 50 60 70 80 90 100 110 50 60 70 80 90 100 frequency [khz] i comp [ a] NCP1060 ncp1063 figure 38. ipk set?point is frozen at lower power demand. 0 100 200 300 400 500 600 700 800 900 40 50 60 70 80 90 100 110 current set point [ma] i comp [ a] NCP1060 ncp1063
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 22 figure 39. ipk set?point is frozen at lower power demand (i lmop 285 a) 0 50 100 150 200 250 300 350 40 50 60 70 80 90 100 110 current set point [ma] i comp [ a] NCP1060 ncp1063 feedback and skip figure 40 depicts the relationship between comp pin voltage and current. the comp pin operates linearly as the absolute value of comp current (i comp ) is above 40 a. in this linear operating range, the dynamic resistance is 17.7 k typically (r comp(up) ) and the effective pull up voltage is 2.7 v typically (v comp(ref) ). when i comp is decreases, the comp voltage will increase to 3.2 v. figure 40. comp pin voltage vs. current 0 0.5 1 1.5 2 2.5 3 3.5 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 v comp [v] i comp [ a ] figure 41 depicts the skip mode block diagram. when the comp current information reaches i compskip , the internal clock setting the flip?flop is blanked and the internal consumption of the controller is decreased. the hysteresis of internal skip comparator is minimized to lower the ripple of the auxiliary voltage for v cc pin and v out of power supply during skip mode. it easies the design of v cc over load range.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 23 jittering osc foldback skip cs comparator drv stage comp s r q q v comp(ref) r comp(up) i compskip figure 41. skip cycle schematic ilimit and opp function the function makes the integrated circuit more flexible. the current drawn out of lim/opp pin defines the current set point. figure 42. ipk set?point dependence on i lmop current 0 100 200 300 400 500 600 700 800 900 0 50 100 150 200 250 300 350 current set point [ma] i lmop [ a] NCP1060 ncp1063 there are several known ways to implement over power protection (opp), all suffering from particular problems. these problems range from the added consumption burden on the converter or the skip?cycle disturbance brought by the current?sense offset. a way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. during the power switch on?time, this point dips to ?nv in , n being the turns ratio between the primary winding and the auxiliary winding. the negative plateau on auxiliary winding will have an amplitude dependant on the input voltage. resistors r oppu and r oppl (figure 43) define current drawn from lim/opp and the negative voltage on auxiliary winding. the negative voltage is tied up with bulk voltage, so the higher the bulk voltage is, the deeper is the negative voltage on auxiliary winding, the higher current is drawn from lim/opp pin and the lower the peak current is. during the internal mosfet off period, voltage on auxiliary winding is positive, but the ic ignores the lim/opp current. the positive lim/opp current has no influence on proper ic function.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 24 s r q i comp to cs setpoint i freeze i pk(0 ) vramp + vsense osc i lmop i lmdec i lmdec i lmop 0 25 a 250 a i pkl i comp mosfet lim/ opp d4 c2 vcc r oppu r oppl aux winding figure 43. the opp circuitry affects the maximum peak current set point ramp compensation and ipk set?point in order to allow the ncp106x to operate in ccm with a duty cycle above 50%, a fixed slope compensation is internally applied to the current?mode control. here we got a table of the ramp compensation, the initial current set point, and the final current set?point of different versions of switcher. NCP1060 ncp1063 f sw 60 khz 100 khz 60 khz 100 khz s a 8.4 ma/ s 14 ma/ s 15.6 ma/ s 26 ma/ s i pk(duty =50%) 250 ma 650 ma i pk(0) 300 ma 780 ma figure 44 depicts the variation of i pk set?point vs. the power switcher duty ratio, which is caused by the internal ramp compensation. figure 44. i pk set?point varies with power switch on time, which is caused by the ramp compensation. 0 100 200 300 400 500 600 700 800 900 0% 10% 20% 30% 40% 50% 60% 70% ipk set-point [ma] dutty rati o [%] NCP1060 ncp1063 fb pin function the fb pin is used in non isolated smps application only. portion of the output voltage is connected into the pin. the voltage is compared with internal v ref (3.3 v) using operation transconductance amplifier (figure 45). the otas output is connected to comp pin. the ota output is accessible through the comp pin and is used for the loop compensation, usually an rc network. the current capability of ota is limited to ?150 a typically. the positive current is defined by internal r comp(up) resistor and v comp(ref) voltage. if fb path loop is broken (i.e. the fb pin is disconnected), an internal current i fb (1 a typ.) will pull up the fb pin and the ic stops switching to avoid uncontrolled output voltage increasing. in isolated topology, the fb pin should be connected to gnd pin. in this configuration no current flows from ota to comp pin (ota is disabled) so the ota has no influence on regulation at all.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 25 fb comp r comp (up ) ota i fb v comp (ref ) v ref i otalim i comp ota out = 0 a if fb = 0 v figure 45. fb pin connection design procedure the design of an smps around a monolithic device does not differ from that of a standard circuit using a controller and a mosfet. however, one needs to be aware of certain characteristics specific of monolithic devices. let us follow the steps: v in min = 90 vac or 127 vdc once rectified, assuming a low bulk ripple v in max = 265 vac or 375 vdc v out = 12 v p out = 5 w operating mode is ccm = 0.8 1. the lateral mosfet body?diode shall never be forward biased, either during start?up (because of a large leakage inductance) or in normal operation as shown in figure 46. this condition sets the maximum voltage that can be reflected during toff. as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you thus must adopt a turn ratio which adheres to the following equation: n v out v f v in,min (eq. 2) 2. in our case, since we operate from a 127 v dc rail while delivering 12 v, we can select a reflected voltage of 120 v dc maximum. therefore, the turn ratio np:ns must be smaller than v reflect v out v f 120 12 0.5 9.6ornp:ns 9.6. here we choose n = 8 in this case. we will see later on how it affects the calculation. 1.004m 1.011m 1.018m 1.025m 1.032m ?50.0 50.0 150 250 350 > 0 !! figure 46. the drain?source wave shall always be positive
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 26 figure 47. primary inductance current evolution in ccm 3. lateral mosfets have a poorly doped body?diode which naturally limits their ability to sustain the avalanche. a traditional rcd clamping network shall thus be installed to protect the mosfet. in some low power applications, a simple capacitor can also be used since v drain,max v in n v out v f i peak l f c tot (eq. 3 ) where l f is the leakage inductance, c tot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), n the n p :n s turn ratio, v out the output voltage, v f the secondary diode forward drop and finally, i peak the maximum peak current. worse case occurs when the smps is very close to regulation, e.g. the v out target is almost reached and i peak is still pushed to the maximum. for this design, we have selected our maximum voltage around 650 v (at v in = 375 vdc). this voltage is given by the rcd clamp installed from the drain to the bulk voltage. we will see how to calculate it later on. 4. calculate the maximum operating duty?cycle for this flyback converter operated in ccm: d max n v out v f n v out v f v in,min (eq. 4) 1 1 v in,min n (v out v f ) 0.44 5. to obtain the primary inductance, we have the choice between two equations: l v in d 2 f sw k p in (eq. 5) where k i l i lavg and defines the amount of ripple we want in ccm (see figure 47). ? small k: deep ccm, implying a large primary inductance, a low bandwidth and a large leakage inductance. ? large k: approaching dcm where the rms losses are worse, but smaller inductance, leading to a better leakage inductance. from equation 6, a k factor of 1 (50% ripple), gives an inductance of: l ( 127 0.44 ) 2 60k 1 5 10.04 mh i l v in d l f sw 127 0.44 10.04m 60k 92.8 ma peak to peak the peak current can be evaluated to be: i peak i avg d i l 2 49.2 m 0.44 92.8 m 2 158 ma on i l , i lavg can also be calculated: i lavg i peak
i l 2 158m
92.8m 2 111.6 ma 6. based on the above numbers, we can now evaluate the conduction losses: i d,rms d i peak 2
i peak i l i l 2 3 0.44 0.158 2
0.158 0.0928 0.0928 2 3 57 ma if we take the maximum r ds(on) for a 125 c junction temperature, i.e. 34 , then conduction losses worse case are: p cond i d,rms 2 r ds(on) 110 mw 7. off?time and on?time switching losses can be estimated based on the following calculations: p off i peak v bulk v clamp t off 2t sw 0.158 ( 127 100 2 ) 10n 2 16.7 15.5 mw (eq. 6) where, assume the v clamp is equal to 2 times of reflected voltage.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 27 p on i valley v bulk n (v out v f ) t on 6 t sw 0.0464 (127 100) 10 n 6 16.7 2.1 mw (eq. 7) it is noted that the overlap of voltage and current seen on mosfet during turning on and off duration is dependent on the snubber and parasitic capacitance seen from drain pin. therefore the t off and t on in equation 7 and equation 8 have to be modified after measuring on the bench. 8. the theoretical total power is then 117 + 15.5 + 2.1 = 127.6 mw 9. if the ncp106x operates at dss mode, then the losses caused by dss mode should be counted as losses of this device on the following calculation: p dss i cc1 v in.max 0.8m 375 300 mw (eq. 8) mosfet protection as in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the mosfet bvdss which is 700 v. figure 48 a?b?c present possible implementations: figure 48. a, b, c : different options to clamp the leakage spike figure 48a: the simple capacitor limits the voltage according to the lateral mosfet body?diode shall never be forward biased, either during start?up (because of a large leakage inductance) or in normal operation as shown by figure 46. this condition sets the maximum voltage that can be reflected during t off . as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you must adopt a turn ratio which adheres to the following equation 3. this option is only valid for low power applications, e.g. below 5 w, otherwise chances exist to destroy the mosfet. after evaluating the leakage inductance, you can compute c with (equation 4). typical values are between 100 pf and up to 470 pf. large capacitors increase capacitive losses... figure 48b: the most standard circuitry is called the rcd network. you calculate r clamp and c clamp using the following formulae: r clamp 2 v clamp v clamp n (v out v f ) l leak i leak 2 f sw (eq. 9) c clamp v clamp v ripple f sw r clamp v clamp is usually selected 50?80 v above the reflected value n x (v out + v f ). the diode needs to be a fast one and a mur160 represents a good choice. one major drawback of the rcd network lies in its dependency upon the peak current. w orse case occurs when i peak and v in are maximum and v out is close to reach the steady?state value. figure 48c: this option is probably the most expensive of all three but it offers the best protection degree. if you need a very precise clamping level, you must implement a zener diode or a tvs. there are little technology differences behind a standard zener diode and a tvs. however, the die area is far bigger for a transient suppressor than that of zener. a 5 w zener diode like the 1n5388b will accept 180 w peak power if it lasts less than 8.3 ms. if the peak current in the worse case (e.g. when the pwm circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 w, then the diode will be destroyed when the supply experiences overloads. a transient suppressor like the p6ke200 still dissipates 5 w of continuous power but is able to accept surges up to 600 w @ 1 ms. select the zener or tvs clamping level between 40 to 80 volts above the reflected output voltage when the supply is heavily loaded. as a good design practice, it is recommended to implement one of this protection to make sure drain pin voltage doesn?t go above 650 v (to have some margin between drain pin voltage and bvdss) during most stringent operating conditions (high vin and peak power).
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 28 power dissipation and heatsinking the ncp106x welcomes two dissipating terms, the dss current?source (when active) and the mosfet. thus, p tot = p dss + p mosfet . it is mandatory to properly manage the heat generated by losses. if no precaution is taken, risks exist to trigger the internal thermal shutdown (tsd). to help dissipating the heat, the pcb designer must foresee large copper areas around the package. take the pdip?7 package as an example, when surrounded by a surface approximately 200 mm 2 of 35 m copper, the maximum power the device can thus evacuate is: p max t jmax
t ambmax r ja (eq. 10) which gives around 870 mw for an ambient of 50 c and a maximum junction of 150 c. if the surface is not large enough, the r ja is growing and the maximum power the device can evacuate decreases. figure 49 gives a possible layout to help drop the thermal resistance. figure 49. a possible pcb arrangement to reduce the thermal resistance junction?to?ambient bill of material: c1 bulk capacitor, input dc voltage is connected to the capacitor c2, r1, d1 clamping elements c3 vcc capacitor ok1 optocoupler r2 resistor to setting i peak current table 5. ordering information device frequency r ds(on) brown in package type shipping NCP1060ap060g 60 khz 34 yes pdip?7 (pb?free) 50 units / rail NCP1060ap100g 100 khz 34 yes 50 units / rail NCP1060ad060r2g 60 khz 34 yes soic?10 (pb?free) 2500 / tape & reel NCP1060ad100r2g 100 khz 34 yes 2500 / tape & reel NCP1060bd060r2g 60 khz 34 no 2500 / tape & reel ncv1060bd060r2g* 60 khz 34 no 2500 / tape & reel NCP1060bd100r2g 100 khz 34 no 2500 / tape & reel ncp1063ap060g 60 khz 11.4 yes pdip?7 (pb?free) 50 units / rail ncp1063ap100g 100 khz 11.4 yes 50 units / rail ncp1063ad060r2g 60 khz 11.4 yes soic?16 (pb?free) 2500 / tape & reel ncv1063ad060r2g* 60 khz 11.4 yes 2500 / tape & reel ncp1063ad100r2g 100 khz 11.4 yes 2500 / tape & reel *ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 29 package dimensions pdip?7 (pdip?8 less pin 6) case 626a issue c 14 5 8 b2 note 8 d b l a1 a eb e a top view c seating plane 0.010 ca side view end view end view with leads constrained notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs?3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension eb is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 m 8x c d1 b h note 5 e e/2 a2 note 3 m b m note 6 m dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.355 0.400 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 9.02 10.16 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 30 package dimensions soic?10 nb case 751bq issue b seating plane 1 5 6 10 h x 45 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.10mm total in excess of ?b? at maximum material condition. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15mm per side. dimensions d and e are de- termined at datum f. 5. dimensions a and b are to be determ- ined at datum f. 6. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. d e h a1 a dim d min max 4.80 5.00 millimeters e 3.80 4.00 a 1.25 1.75 b 0.31 0.51 e 1.00 bsc a1 0.10 0.25 a3 0.17 0.25 l 0.40 0.80 m 0 8 h 5.80 6.20 c m 0.25 m dimension: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.37 ref l2 0.25 bsc a top view c 0.20 2x 5 tips a-b d c 0.10 a-b 2x c 0.10 a-b 2x e c 0.10 b 10x b c c 0.10 10x side view end view detail a 6.50 10x 1.18 10x 0.58 1.00 pitch recommended 1 l f seating plane c l2 a3 detail a d
NCP1060, ncv1060, ncp1063, ncv1063 www. onsemi.com 31 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint 16 89 8x on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP1060/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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